This invention relates generally to clocking circuits and more particularly, to a method and apparatus for controlling the data rate of a clocking circuit.
Communications between electrical circuits generally require that the circuit receiving the data must be able to receive the data at the same rate and time that the sending circuit transmits it. Discrepancies in the data rate or time of communication between the two circuits can lead to errors or loss of data.
Clocking circuits have traditionally operated at one of two classes of data rates: a single data rate, clocking on one edge of a primary clock, or a double data rate, clocking on both edges of the primary clock. This results in three types of circuits: a circuit that clocks on the rising edge of the primary clock, a circuit that clocks on the falling edge, or a circuit that clocks on both rising and falling edges.
Problems can arise when a circuit of one type tries to communicate with a circuit of another type. In one situation, the transmitting circuit attempts to transfer data at a different rate than the receiving circuit can handle, such as a double data rate processor circuit transmitting to a single data rate SDRAM. When the transmitting circuit transfers data at a faster rate than the receiving circuit can handle, the receiving circuit can miss portions of the data. For example, if a transmitting circuit transmits data at a rate of 66 MHz, while the receiving circuit receives data at 33 MHz, the receiving circuit will at best receive half of the data transmitted (rate of data received/rate of data sent=33 MHz/66 MHz=xc2xd).
In another situation, the receiving circuit may only xe2x80x9creadxe2x80x9d the data at a given point in time, and for a given duration. If the data is not present during that time, it may not be received. Here, the transmitting circuit may transmit data on one edge of the primary clock, such as the rising edge, while the receiving circuit xe2x80x9creadsxe2x80x9d the data on the other edge of the clock, such as the falling edge.
One solution to this problem is the addition of a latch circuit between the transmitting circuit and the receiving circuit. A latch maintains a data signal until it is overwritten by a new data signal. Thus, data can be held until the receiving circuit is ready to xe2x80x9creadxe2x80x9d it. The problem with this solution is that this requires additional circuitry; circuitry that takes up space and requires additional power. This is the antithesis of the goals of modem circuit design, which is to minimize the amount of circuitry and power usage.
These problems are particularly prevalent for communications in a synchronous dynamic random access memory (SDRAM). A SDRAM can use all or some of the three clocking protocols discussed above: clocking on the rising edge of a clock signal, the falling edge, or both edges. Similarly, a processor, or more specifically, a memory controller, that communicates with and controls the SDRAM can use all or some of the same three clocking protocols. In order for a given SDRAM to efficiently communicate with a given memory controller, the two circuits must use the same clocking protocol, sending and receiving data at the same rate and time, i.e., both clocking on the same edge or edges of the same clock signal. Thus, the need to match clocking protocols limits the memory controllers that can be used with a given SDRAM.
In the past, proper communication between a given memory controller and the SDRAM has been ensured by producing several types of SDRAMs, each of which uses a single clocking protocol. This solution, however, requires that several different types of SDRAMs and compatible memory controllers be available, and results in an unnecessarily expanded product line by manufacturers and sellers of SDRAMs and memory controllers.
Therefore, there is a need for a single SDRAM or clocking circuit that is capable of operating on either or both edges of a clock signal, for communications with memory controllers having varying data rates and times of communication.
The present invention provides a method and apparatus for producing a programmable clocking circuit that is capable of operating at either a single data rate or a double data rate and on either the rising or falling edge of a clock signal. A single data rate circuit is a circuit that clocks once per clock cycle, typically on only one edge of a clock signal (rising or falling), while a double data rate circuit clocks twice per clock cycle, typically on both edges (rising and falling) of a clock signal. The double data rate circuit clocks twice as often as the single data rate circuit, hence the name. According to one embodiment of the invention, a clocking circuit receives a first clock signal, and a switching circuit receives a second clock signal. The switching circuit is programmable to couple either the first clock signal to the clocking circuit or a steady state voltage to the clocking circuit. The clocking circuit is structured to clock on the transitions of the first clock signal to both logic levels, typically a logic zero and logic one, in response to receiving the second clock signal from the switching circuit, and clocking on the transition of the first clock signal to only one logic level in response to receiving the steady state voltage from the switching circuit. The data rate and time for communication for the clocking circuit can then be selected by programming the switching circuit to either couple the second clock signal or the steady state voltage to the clocking circuit.